1. Field of the Invention
This invention relates to CMOS FET semiconductor memory and logic devices with enhanced ESD (ElectroStatic Discharge) performance and more particularly to the source and drain regions structures therein and methods of manufacture thereof.
2. Description of Related Art
1. The reduced drain doping concentration in deep submicron transistors reduces substrate current, and delays the snapback effect.
2. An ESD deep-drain-implant cannot be used due to significant punchthrough effect between source and drain.
U.S. Pat. No. 5,595,919 of Pan for "Method for Making Self-Aligned Halo Process for Reducing Junction Capacitance" describes an LDD structure made using a self-aligned halo process.
U.S. Pat. No. 5,496,751 of Wei et al. for "Method of Forming an ESD and Hot Carrier Resistant Integrated Circuit Structure" describes a method of forming an ESD circuit having LDD regions (preferably formed by LATID) and DDD regions. Among other things, this reference differs from the counter Halo/drain halo regions of the present invention.
U.S. Pat. No. 5,650,340 of Burr et al. for "Method of Making Asymmetric Low Power MOS Devices" teaches a low threshold voltage MOS devices having asymmetric halo implants. An asymmetric halo implant provides a pocket region (P+) located under the source region or under the drain region of a device.
U.S. Pat. No. 5,534,449 of Dennison et al. for "Methods of Forming Complementary Metal Oxide Semiconductor CMOS Integrated Circuitry" describes a method of forming CMOS integrated circuitry having four doped regions comprising the source/drain regions.
A problem with the prior art in view of trends to greater degrees of miniaturization is that junction leakage and junction short circuits to the substrate are more and more likely to occur in advanced technology devices as the dimensions of the devices forming those circuits become smaller and smaller.